There has been a lot of talk about the improved pinout, especially moving the low-side switch controls from PB13-15 to the alternate function locations PA7,PB0,PB1. If I understood the response from ST quoted in this thread, there would be some ~120ns less propagation delay on these lines. I have tried to understand this, and especially how it would affect the performance of the drive so significantly as it is said here. I tried reading the thread (which isn't a one night task any more ) but I haven't found any technical discussion about this.
First, I tried measuring the complementary PWM outputs. I have my controller wired "the wrong way", similarly to Mihai's original schematic, i.e pins PA8-PA10 for high side switches and PB13-PB15 for low side. My drive method (and I think Mihai's too) is something that is referred as Complementary High-Side PWM (referring to this excellent application note by SiLabs: https://www.silabs.com/Support%20Doc...Docs/AN794.pdf figure 9). The STM32 PWM generator has adjustable non-overlapping time and I've set it to be seven clock cycles, which corresponds to 98ns with 72MHz clock. And by measuring the complementary outputs, I see that non-overlapping time is something close to 100ns on both rising and falling edge of the high side control. (My 50MHz scope is on the limits here). Now, if the improved pinout is applied, so that suddenly the low side control would have 120ns less propagation delay, it would imply that both rising and falling edge of the low side control would come 120ns earlier, meaning that the non-overlapping time on the other edge of the PWM would become much larger, like 220ns and on the other edge the non-overlapping time would become negative causing possibly a short circuit in the drive stage. So practically you would have to increase the intentional non-overlapping time in the software to make sure that both controls are not high at the same time. I don't understand how this would be beneficial. The way I see it, the drive signal delays are very nicely balanced with the current schematic.
Secondly, even though it would be so that the alternative pinout would provide the delta of ~120ns towards something that is better, I simply cannot see the significance of it. At least I am driving the PWM at 20kHz. The period is then 50us or 50000ns. So we are talking about timing issues that are 0.24% of the PWM period. I don't know that much about motor control, but I think that's negligible.
Sorry for the long post, but I've been thinking and studying this and I would really appreciate if there was discussion or an explanation why the alternative pinout is better. And even better, a measurement results or scope waveforms from the PWM signals. I can try to capture the scope waveforms from my boards if that is wanted.
Thanks,
-roivai